In general, the output clock frequency of a PLL is fixed to a value obtained by dividing the frequency of an input clock by the division ratio of a PLL divider. For example, an integer-N PLL indicates a PLL where N is an integer. When the input frequency of the integer-N PLL is 40 MHz and the division ratio N of the divider is 8, the output frequency of the PLL is fixed to 320 MHz.
On the other hand, a fractional-N PLL (frequency synthesizer) includes a divide which has a division ratio consisting of an integer and a decimal fraction, and a fractional number k controls the decimal fraction. Thus, although the input frequency of the fractional-N PLL is fixed to 40 MHz, the PLL in which the division ratio N of the divider is set to (8+fractional number k) can control k. Therefore, an arbitrary frequency between 320 MHz and 360 MHz can be generated as the output frequency.
However, since a divider capable of implementing a decimal frequency does not exist in reality, a divider with a division ratio of N and a divider with a division ratio of N+1 must be alternately used in order to implement a frequency synthesizer which outputs a decimal frequency.
Thus, the frequency synthesizer has a basic structure which is based on the basic structure of an integer-N PLL, uses a divider for dividing N or (N+1) frequency instead of a divider of which the division ratio is N, and additionally includes a DSM (Delta-Sigma Modulator) to select the N or (N+1) frequency.
As such, the conventional frequency synthesizer locks the phase and frequency of an output clock to the average of a clock divided by N and a clock divided by (N+1). Thus, the conventional frequency synthesizer requires quite a long time for frequency locking.
Furthermore, since the conventional frequency synthesizer includes a plurality of blocks, the power consumption is increased by the blocks.